The present invention relates to the testing of logic circuits and, more particularly, to a method for testing a logic circuit which has a built-in scan circuit for a diagnosis.
A logic circuit of a scale larger than a certain degree is constructed of a plurality of logic blocks (each block including a plurality of combinational logic circuit stages) which are interconnected through data holding stages (such as flip-flops or latches). The logic circuit of a specified type which is formed as an LSI or which is mounted on a printed circuit board is ordinarily provided with a scan circuit which directly controls the respective data holding stages in order to set diagnostic input data and to read out diagnostic output data, and the logic block and the scan circuit are activated during exclusive time periods with respect to each other, in other words, so that while one is operating, the other is kept in an non-operating state, by a signal which is applied to a scan enable edge pin.
According to a prior-art method for diagnosing or testing the logic circuit of the above type, as described in Japanese Patent Application Laid-open No. 60-102021, the entire circuit is logically divided into partial circuits each consisting of one of the logic blocks, an input side data holding stage and an output side data holding stage thereof, and a scan circuit segment associated with them. Subsequently, in each of the partial circuits, the scan circuit segment is actuated to set diagnostic input data in the input side data holding stage, and then the operation of the scan circuit segment is inhibited while the logic block is actuated. Thereafter the output of the logic block set in the output side data holding stage is read out as diagnostic data. Although this method is intended to obtain the diagnostic data for the logic circuit section composed of the logic blocks and the data holding stages, it cannot produce diagnostic data for the scan circuit section (including the various edge pins connected to the scan circuit). Therefore, if the scan circuit section is faulty, a correct diagnosis cannot be drawn from the diagnostic data obtained in the foregoing way. Accordingly, satisfactory diagnostic data cannot be produced without the diagnostic data for the scan circuit section also.